1. Field of the Invention
The invention relates to an electronic component and a method of manufacturing the same and, in particular, an electronic component incorporating a coil and a method of manufacturing the same.
2. Description of the Related Art
One known traditional electronic component is a multilayer chip inductor described in Japanese Unexamined Patent Application Publication No. 2005-191191. The multilayer chip inductor described in this patent document is explained below with reference to the drawings. FIGS. 9A and 9B illustrate multilayer chip inductors 500 and 600, as seen through from the direction of layering.
As illustrated in FIG. 9A, the multilayer chip inductor 500 includes a multilayer structure 502. The multilayer structure 502 incorporates a coil L, as illustrated in FIG. 9A. The coil L is configured such that a plurality of coil conductors 504 are connected together by a via-hole conductor (not illustrated). The coil L forms a substantially rectangular loop path composed of short sides L1 and L2 and long sides L3 and L4 by the plurality of coil conductors 504 overlapping each other, as illustrated in FIG. 9A.
The multilayer structure 502 further incorporates lead-out conductors 506a and 506b. The lead-out conductors 506a and 506b are extended out to side faces of the multilayer structure 502 and connected to external electrodes (not illustrated) and also connected to the coil L.
The coil L in the multilayer chip inductor 500 illustrated in FIG. 9A includes lands 508a and 508b. The lands 508a and 508b are portions in the coil L that are connected to a via-hole conductor. The via-hole conductor may preferably be thick to reliably connect the coil conductors 504, so the lands 508a and 508b are wider than the line width of each of the coil conductors 504. The lands 508a and 508b protrude toward outside the loop path at the long sides L3 and L4, as illustrated in FIG. 9A. This can prevent the area inside the coil L (that is, the area of a section surrounded by the loop path) from being reduced by protrusion of the lands 508a and 508b toward inside the loop path. In other words, the multilayer chip inductor 500 can avoid causing a reduction in the value of inductance of the coil L to some extent.
However, the multilayer chip inductor 500 illustrated in FIG. 9A still has the problem of reduction in the value of inductance of the coil L. More specifically, the lands 508a and 508b protrude toward outside the loop path at the long sides L3 and L4. Therefore, the distance W1 between a side face of the multilayer structure 502 and each of the long sides L3 and L4 is smaller by the amount of the protrusion of each of the lands 508a and 508b than that which would occur if the lands 508a and 508b did not exist. The distance W1 needs to have a sufficient length in order to prevent the coil L from being exposed from the side face of the multilayer structure 502. Therefore, as illustrated in FIG. 9A, when the lands 508a and 508b protrude from the long sides L3 and L4, respectively, it is necessary to displace each of the long sides L3 and L4 by the amount of the protrusion of each of the lands 508a and 508b toward the inner portion of the multilayer structure 502. As a result, the area inside the coil L is smaller by the amount of an area twice the product of the length of each of the long sides L3 and L4 and the protrusion of each of the lands 508a and 508b than that which would occur if the lands 508a and 508b did not exist. This results in a reduction in the value of inductance of the coil L.
For a multilayer chip inductor 600 illustrated in FIG. 9B, lands 608a and 608b protrude toward outside the loop path at the short sides L1 and L2. Also in this case, it is necessary to displace the short sides L1 and L2 toward the inner portion of a multilayer structure 602 by the amount of the protrusion of the lands 608a and 608b. Accordingly, the area inside the coil L of the electronic component 600 is smaller by an area twice the product of the length of each of the short sides L1 and L2 and the protrusion of each of the lands 608a and 608b than that which would occur if the lands 608a and 608b did not exist.
The length of each of the short sides L1 and L2 is smaller than the length of each of the long sides L3 and L4. Hence, the amount of reduction in the area inside the coil L in the multilayer chip inductor 600 illustrated in FIG. 9B is smaller than that in the multilayer chip inductor 500 illustrated in FIG. 9A. Accordingly, the reduction in the area inside the coil L in the multilayer chip inductor 600 is suppressed more than that in the multilayer chip inductor 500. In other words, the reduction in the value of inductance of the coil L in the multilayer chip inductor 600 is suppressed more than that in the multilayer chip inductor 500.
However, the multilayer chip inductor 600 illustrated in FIG. 9B has the problem of increase in stray capacitance occurring in the coil L, as described below. More specifically, as illustrated in FIG. 9B, the lands 608a and 608b overlap lead-out conductors 606a and 606b, respectively, in plan view from the direction of layering. Hence, stray capacitance occurs between the lands 608a and 608b and the conductors 606a and 606b, and thus stray capacitance of the coil L increases. As a result, the Q value of the coil L decreases.